Vlint Release Notes
---------------------------
Release 3.3.Beta
----------------

Release 3.3.Beta under the Linux OS is a port of release 3.2x to 
Red Hat Linux Enterprise 3. 
As such it contains only minor bug-fixes and enhancements over 
releases 3.2d on RHL 7.3 and 3.2f under Windows.

I) Enhancements
---------------

Vlint 3.3.Beta contains the following enhancements that are not yet listed in
the User Guide:

1. Verilog 2001 Generate Statements
2. Verilog 2001 Multidimensional Arrays
3. Verilog 2001 config block support
4. Verilog-2001 initial value specified in variable declarations
5.  Verilog-2001 signed bit-strings support
6. Configuration file must now be specified with .cfg extension on command line
7. Combining the -net and -v command line options supported
8. New Interactive Tcl Commands Added
9. Global disable for embedded filter directives
10. Vlint Embedded filter directives
11. Traversing up one hierarchy level when viewing results
12. Changing the width of display of results
13.  Initial blocks are now expanded
14. 'protected and  `endprotected compiler directives support
15.  Wires declared with constant driven values will be treated as constants
16.  Procedural continuous assignments support 
17. "Clear All" button added to "File->Design" (add design files) dialog
18. Multiple file selection from Verilog file list via "Add File" 
19.  Vlint now reports SystemVerilog constructs.
20. C-Style Comment PSL Assertions Support
21. Enhanced Case statement reports
22. Port Size Mismatch Report Changed
23. Support for excluding messages about specific files
24. Selecting start-up working directory
25. End-point filters
26. Browse information
27. Non-blocking assignments in combinational blocks
28. Report synchronous resets
29. Include `defined file

Details of these enhancements are given below.

1. Verilog 2001 Generate Statements
------------------------------------
Verilog 2001 generate statements are now supported.

2. Verilog 2001 Multidimensional Arrays
---------------------------------------
Verilog 2001 multidimensional arrays are now supported.

3. Verilog 2001 config block support
------------------------------------------

  Vlint now ofers the following limited support for the Verilog 2001 
  config statement. 
  The config statement can be used to define the top-level module name 
  for a design, in a tool-independent manner, and an optional list of
  include library files search paths. Furthermore, users may specify 
  configuration information for any module instances. 

  The current implementation supports the following statements in 
  a Verilog-2001 config block:

  a.  design <top-module name> ';'

     Allows users to Specify the top-level module name for a design
     to be analyzed. Since  a top-module name may be specified to
     vlint in several ways, if conflicting top-module names are
     found,  vlint will determine the top module name to be
     used in the following way:

         1.  Use the name specified via the -topmodule <name> 
             command line as the top preference
         2.  Use the name specified via the TOPMODULE: record
             in vlint.atr file as the second preference
         3.  Use the name specified via the design statement
             in a config block as the third preference
         4.  Use the name derived from default search as the
             last resort

   b. default liblist <one or more library aliases>

     Allows users to specify a list of library files search 
     paths. This is similar function to the INCLUDE: record
     in vlint.atr file, except the "library names" specified
     in this statement are just aliases, the actual binding
     of a library alias to a library path name is via the 
     library statement:

        library <library alias>  <library include pathname> ';'

     The library statement is specified in a HDL source file
     outside the config block, and may be specified in one or
     more separate HDL source files from the one which contains
     config block.

     All library search paths specified via the "default liblist"
     statements are append to any include file search paths as
     specified via the INCLUDE: records in vlint.cfg file.

 
   c. An Instance statement in a config block allows users to
      specify how a module instance in a design could be configured.
      The instance statements are parsed by vlint, but its
      data are silently discarded for now.

4. Verilog-2001 initial value specified in variable declarations
----------------------------------------------------------------

     Vlint now supports user specified initial values when
     reg, integer, real, and realtime variables are declared.

     Thus, the following syntax are now accepted in vlint:

 
       reg aVar = 1'b0;
       reg [15:0]  bs = 16'habcd;
       integer limit = 65535;
       real refresh_interval = 12.5;
       realtime stop_clock = 355.6;

     According to Verilog-2001, an initial value specified
     in a reg/integer/real/realtime variable declaration does
     not create a continuous assignment (as in the case of wire
     declaration). Rather the initial values are assigned to the
     variables in the same manner as if they were specified in
     an initial block. Thus, the following code is functionally
     the same as the above example:

      reg aVar;
      reg [15:0] bs;
      integer limit;
      real refresh;
      realtime stop_clock;
    
      initial begin
          aVar = 1'b0;
          bs   = 16'babcd;
          limit = 65535;
          refresh_interval = 12.5;
          stop_clock = 355.6;
      end

5.  Verilog-2001 signed bit-strings support
--------------------------------------------

    Vlint now supports the use of signed bit-strings in HDL code.
    The followings are legal use of signed bit-strings

       wire signed [31:0] abus  = 32'sh12345678;
       parameter signed DD = 1'sb1;

       if (hec != 32'sd598) ....

6. Configuration file must now be specified with .cfg extension on command line
--------------------------------------------------------------------------------

The command line has changed such that is you specify

-ch <file> 

<file> is treated as a design file rather than a configuration file
unless it has the .cfg extension

7. Combining the -net and -v command line options supported
-----------------------------------------------------------
Previously it was not possible to combine the -net and -v 
options. In release 3.2 you can now use both -net and -v on the command line.

8. New Interactive Tcl Commands Added
--------------------------------------
The following interactive Tcl command have been added:

set_attempts n
	Set number of search attempts to n
set_analysis <method>
	Set analysis method to sequential or reachability
	
set_check_option <option>
	Set check option
Examples: 

set_check_option ALN _n
set_check_option CCKN PREFIX 
set_check_option CKN PREFIX clk
set_check_option DANG  MODULE DESIGN
set_check_option FULL_CASE_DIRECTIVE synopsys full_case
set_check_option PARALLEL_CASE_DIRECTIVE synopsys parallel_case
set_check_option RSTNAME PREFIX rst
set_check_option TRANSLATE_ON_DIRECTIVE synopsys translate_on
set_check_option TRANSLATE_OFF_DIRECTIVE synopsys translate_off

read <file>
	Read design file
build
	Build the design
libdir <dir>
library <dir>
	Set library directory

libext <ext>
	Set library files extension
incdir <dir>
	Set include directory
define
	Set definition

9. Global disable for embedded filter directives
------------------------------------------------
You can now globally disable all embedded filter directives
from the command line.

The new command line option to do this is
    -embedded_filters_off
 
You can abbreviate this to
    -emb
Supplying this option turns off all embedded filter directives.


10. Vlint Embedded filter directives
-----------------------------------------
Embedded filter directives may now also be specified using
//vlint check on
//vlint check off
directly in the Verilog RTL.


11. Traversing up one hierarchy level when viewing results
-----------------------------------------------------------
Currently Vlint may report a message relating to a library cell, whereas
you might wish to see the instantiation of the cell, which is one level
up in the hieararchy. If the message contains a hierarchical signal name
you can view the file relating to one level up the hierarchy for this signal.

After invoking the GUI, please make sure that the "Create browse info" box
is checked under General Options from the Edit->Options menu, Click OK and
then you are ready to run. After setting up your checks and running the
application, open up the View->Results windows. There is a new feature 
available by right-clicking on a message containing a hierarchical
signal name in the Messages window. A list of hierarchical names is displayed
in a menu, and by selecting and clicking on one you should go up in the hierarchy
resulting in the display in the File window showing the instantiation of the module.
The default is to go up, but you can toggle this by clicking on the "Go Up" menu
item in the list. Next time you want to select a signal, it should say "Go To".
Note that there are some limitations in dealing with "synthesized" signals that
don't exist as user signals in the net-list,
and that if you try to go up on a top-level signal, nothing changes.
Also right-clicking on a message without a hierarchical name shows nothing,
as does clicking on messages if the browse information has not been created
in a previous run.

If you want to go further up the hierarchy, you can open the design browser
by selecting View->Browse Design and then open the Message View by selecting
View->Results. Now when you right click on a message containing a hierarchical name
and then select the signal in the menu, you should go to the source code in the browser
and be able to go up the hierarchy by clicking on UP.
There is limited viewing capability in the design browser so if you want to see
more than just a portion of the file, you need to left double-click on the appropriate
line in the file window.
Note that you should use a graphical editor such as emacs to go to the corresponding
line of code in the editor. Set your editor to emacs in the View->Preferences
window.
The Browse Design dialog now also accepts a hierarchical name in the "Hiearchical name" text entry
box. However, you must hit return after entering the name. If the name matches a design
name, the the appropriate part of the corresponding design file is shown but if the name
does not match then currently nothing changes.


12. Changing the width of display of results
--------------------------------------------
Lists in the "View->Results" dialog are not currently re-sized automatically as 
the window is re-sized.
To change the results display, edit your ~/.dv.ini file to 
add the following to display wider results

	RESULTS_WIDER 1

or the following to revert to the previous width default

	RESULTS_WIDER 0

or check/uncheck the "Wider Results" option in the "View->Preferences" dialog
and then exit the GUI and re-start it.
You can also manually select your preferred width from the drop-down 
"Results list size" menu in in the "View->Preferences" dialog

13.  Initial blocks are now expanded
------------------------------------
Initial blocks are now expanded, but only simple assignment statements
are synthesized. Any task/function calls, for loops, delay or 
event control constructs are not evaluated.  

Furthermore, signals which are initialized via declaration and/or initial
blocks, but are not driven by other circuit logic will be flagged:

    a. If a signal is initialized via declaration but undriven anywhere else:

       Vlint flags that the signal is undriven but has an initial value 
       assigned via declaration

    b. If a signal is initialized via initial block but undriven anywhere else:
  
       Vlint flags that  the signal is driven solely via initial block only

    c. If a signal is initialized via initial block and declaration: 

       Vlint flags that the signal is initialized via initial block and declaration

14. 'protected and  `endprotected compiler directives support
--------------------------------------------------------------
Vlint will now silently ignore any HDL source code enclosed by the
protected and `endprotected directive, as that code is typically encrypted.

Furthermore, if one or more I/O ports of a module and/or parameter
port list are enclosed in `protected and `endprotected directives,
vlint will mark the module as a black box object, and will not
analyze its content. This is because vlint cannot determine 
accurately the connectivity of the module's instances to the rest
of the design, and by analyzing those instances blindly may cause
many false messages (e.g., dangling signals) to be reported.

15.  Wires declared with constant driven values will be treated as constants
----------------------------------------------------------------------------
Wires declared with constant driven values will be flagged as constant
wires. If they drive any case statements, their constant-driven signal
values will be used to resolve any missing case items or overlapping
case items. 

16.  Procedural continuous assignments support 
----------------------------------------------
Procedural continuous assignments are now expanded and support in vlint.


17. "Clear All" button added to "File->Design" (add design files) dialog
------------------------------------------------------------------------
The"File->Design" (add design files) dialog now has
a "Clear All" button that clears all lists.
   
18. Multiple file selection from Verilog file list via "Add File" 
-----------------------------------------------------------------
To load Verilog files from a Verilog command file-list select the file 
from the "Add File" dialog. The Verilog command file is recognized 
by having an .f extension.

19.  Vlint now reports SystemVerilog constructs.
--------------------------------------------------------------------
Vlint now reports SystemVerilog language constructs.

To enable the recognition of SystemVerilog specific keywords like 
"property", users need to specify the -systemverilog command line
option when compiling HDL sources containing SystemVerilog constructs.

Furthermore, there are now two new optional rules which users may
specify in the vlint.chk file:

      Rule                          Use
    SYSTEMVERILOG        If specified, vlint will flag a warning on
                         any SystemVerilog constructs found in HDL sources

    SYSTEMVERILOG_KWD    If specified, vlint will flag any identifier
                         names (such as property, or sequence) used in
			 HDL sources which are reserved keywords in 
		         SystemVerilog
                         

20. C-Style Comment PSL Assertions Support
------------------------------------------

    Simple PSL assertions can now be specified in Verilog source files in two 
    ways:

    1. Old way: // PSL assert <always|never> [!]<signal_name>

    2. New C-comment style assertions:

       /* PSL  

          { assert  <always|never> [!]*<signal_name> ';' } +

       */
         

      Note that the initial "/*" and "PSL" tokens must be on the
      same line. However, all other tokens can be placed at any 
      different lines, and "// <comment>" may be inserted between
      tokens. 

      Multiple assertions may be specified within one /* PSL ... */
      block.

      This is not a C-comment, only the keyword PSL, assertion
      clauses, and "// <comment>" may be specified between "/* PSL"
      and "*/"

21. Enhanced Case statement reports
-----------------------------------
The following new rule check acronyms have been added:

	AVOID_FULL_CASE
	AVOID_PARALLEL_CASE
	CASE_DEFAULT_IGNORED
	NO_XZ_CASE_ITEMS

Specifying these checks in include checks section
of the .chk file.

Details of the rule checks are as follows:

AVOID_FULL_CASE: Avoid the use of full-case directives
Full case directives may result in incorrect logic synthesis. 
		
		
AVOID_PARALLEL_CASE: Avoid the use of parallel-case directives
Parallel case directives may result in incorrect logic synthesis. 
			
		
CASE_DEFAULT_IGNORED: Report the use of defaults in fully specified case
Default alternatives in fully specified case statements will be ignored
by logic synthesis

NO_XZ_CASE_ITEMS: Report use of X or Z in case statement items
The use of X or Z in case items is not recommended for logic synthesis. 
		
22. Port Size Mismatch Report Changed
--------------------------------------
Port size mismatches involving constants are now only reported 
by default if they involve constant values which would exceed the maximum
valued allowed by the width of the port.
To report all port size mismatches you now must specify the following check option
in the .chk file:

REPORT_ALL_PORT_SIZE_MISMATCHES

23. Support for excluding messages about specific files
-------------------------------------------------------
A new vlint command line option that excludes messages about specified files 
from being reported has been added:

-exclude_file <file_name>

For example, if the file /design/lib.v has been specified in the file list
but you want to exclude it from reports, you would use the following option

-exclude_file "/design/lib.v"

To exclude multiple files, you need to repeat the specification
of the option and file.

24. Selecting start-up working directory
----------------------------------------
In this Preferences dialog you can now select how you want the GUI 
to determine your start-up directory.

Select "Current Directory" if you usually
want to start in the directory from which you invoked the GUI. 

Select "Last Working Directory" if you want the GUI to start 
in the last directory you used as a working directory. 

The default selection is "Automatically Select Directory".

In this case, your last working directory will be selected unless you 
invoke the GUI from a directory that was previously used as a working 
directory and still contains the .inp design set-up file.

File->Working directory now shows a history of the last 10 working 
directories selected - enabling you to quickly revert to a previously
used working directory.

25. End-point filters
---------------------
Click on the "End-Points" button in the Options dialog
to open the End-Point Filters dialog to select end-points to be included 
or excluded from clock domain and timing checks.
The End-Points dialog contains two scrollable windows containing
end-points to be included or excluded.
Wild-cards are supported. 
For example to exclude all end-points in the the CPU block in
a top level design called top, just add top.cpu.* to the exclude list. 
The lists are combined in determining which end-points to filter.
Click on "OK" or "Apply" to register filtered end-points.


26. Browse information
----------------------

If you try to view browse information in the bp GUI before creating it, you are now
asked whether you want to create it automatically. If you respond
yes, then the application is run automatically to create browse information.

27. Non-blocking assignments in combinational blocks
----------------------------------------------------
The NBA check now also reports the use of non-blocking assignments in
combinational always blocks.

28. Report synchronous resets
-----------------------------
You can now report synchronus set/resets by adding the rule acronym:

	SYNCH_SR

to the include checks section of the .chk file.

29. Include `defined file
-------------------------
You can now include a file that was previously defined by `define.
E.g.

`define MYFILENAME my_design.v
`include `MYFILENAME


II) Resolved Issues
-------------------

The following issues are resolved in release 3.3 :

I1. Issue with signed bit string support
I2. Issue with concatenation involving sized negative numbers 
I3. Issue with missing or overlapping case items reporting
I4. Issue with Task output implicit declarations
I5. Issue with fully specified case statement
I6. Issue with handling of $signed/$unsigned type-casts
I7. Issue with handling of "\" 
I8. Issue with multiple file selection in GUI via "Add File"
I9.  Issue with multiple drivers caused by resettable DFFs 

Details of these issues are given below.

I1. Issue with signed bit string support
----------------------------------------
Previously signed bit strings would result in a syntax error.
This issue is now resolved.

I2. Issue with Concatenation involving sized negative numbers
-------------------------------------------------------------
Previously, sized negative numbers in concatenations with sized
positive numbers were treated as unsized i.e. 32 bits.
Incorrectly reported mismatching bit assignments resulting from  
concatenations of sized negative numbers and positive numbers are now 
resolved. 

I3. Issue with missing or overlapping case items reporting
-----------------------------------------------------------
The reporting of missing or overlapping case items now report the
location of the case statement head.


I4. Issue with Task output implicit declarations
------------------------------------------------
Issue with Task output implicit declarations resulting in an error
has now been resolved.

I5. Issue with fully specified case statement
---------------------------------------------
An issue with a case item being missed during the case item "coverage" 
check for large fully specified case statements has been resolved.
This issue resulted in the assumption of an incomplete case statement and, hence, 
an inferred latch.

I6. Issue with handling of $signed/$unsigned type-casts
-------------------------------------------------------
Signed/unsigned typecasts would result in an error.
Verilog 2001 $signed/$unsigned type-casts are now accepted.

I7.  Issue with handling of "\" 
-------------------------------
The use of "\" in definitions was not accepted and would result
in an error. This issue has been resolved

I8.  Issue with multiple file selection in GUI via "Add File"
-------------------------------------------------------------
A problem with multiple file selection in the GUI on Linux/Solaris
via "Add File" has been resolved.

		
I9.  Issue with multiple drivers caused by resettable DFFs 
----------------------------------------------------------
A problem with multiple drivers caused by the use of separate for loops
to specify D type flip-flops and their reset operation has now been resolved.
extern unsigned int bit_array[];



Copyright Blue Pearl Software Inc. 2005