RUNNING FSM EXAMPLE USING DIFFERENT SIMULATORS

CONTENTS

STEPS FOR SIMULATING USING FINSIM (FINTRONIC)
STEPS FOR SIMULATING USING VSIM (MODELTECH)
STEPS FOR SIMULATING USING VCSI (SYNOPSYS)
STEPS FOR SIMULATING USING NCSIM (CADENCE)
STEPS FOR SIMULATING USING NC Verilog XL (CADENCE)
STEPS FOR SIMULATING USING NC Verilog (CADENCE)
STEPS FOR SIMULATING USING Verilog-XL (CADENCE)

This README presents step-by-step instructions to simulate the Verilog design (FSM example) using various simulators like FINSIM, VSIM, VCSI, NCSIM, NC Verilog XL, NC Verilog and Verilog XL.

I) STEPS FOR SIMULATING USING FINSIM (FINTRONIC):

1)Source environment variables

For example,

./envsource

envsource has all the environment variables set up. You can change the paths accordingly.

Make sure you set the FINUSERPLIOBJ environment variable as follows:

setenv FINUSERPLIOBJ "<path>/vtplifinsim.o <path>/vt_finsimuser.o"

vt_finsimuser.o and vtplifinsim.o are available in our PLI directory. Make sure

the path to the PLI directory is specified.

---------------envsource file contents------------------------------------------------------------------

setenv FINTRONIC <path where Finsim is installed>

setenv FIN_OBJECT_PATH $FINTRONIC/obj/gcc

setenv FIN_INCLUDE_PATH $FINTRONIC/include

setenv FIN_LIBRARY_PATH $FINTRONIC/lib/gcc

setenv FINTEMPDIR ./fintmp

setenv FIN_COMPILER gcc

#setenv FINUSERPLIOBJ "<path_to>/vtplifinsim.o <path_to>/vt_finsimuser.o"

#NOTE: The path and the files are within "" separated by a space.

setenv FINUSERPLIOBJ "$UT_ROOT_DIR/PLI/vtplifinsim.o $UT_ROOT_DIR/PLI/vt_finsimuser.o"

setenv FIN_LICENSE_PATH $FINTRONIC/env

#setenv _ULKFLAGS "-lnsl -lsocket -lintl"

#Above setenv is for SOLARIS ONLY!

setenv FINSYSPLIOBJ $FIN_OBJECT_PATH/verisim.o

setenv $UT_ROOT_DIR <path_to directory holding Undertow distribution>

----------------------------------------------------------------------------------------------------------------

2)Add to source code close to top module

initial

begin

$vtDumpvars();

end

In this example, the above has been inserted in 'top.v' file.

3)Modify 'top.cf' file, for example:

-a +vtdbg -ptab vt_ptab

-f source +VTCOMPRESS250 +VTVECTORVALUES

where:

a) -a : suppresses all warning messages

b) +vtdbg : generates information for Veritool's source level debugger

c) -ptab <file> : gets information about pli tasks/functions from the specified ascii file instead of having to link user's pli object files to obtain this information. vt_ptab is available in our PLI directory. Make sure the path to this directory is specified.

d) -dsm <mode> : sets the default simulation mode to compile (-dsm com) or interpret (-dsm int), -dsm com is the default

e) -f <file> : used to specify file that contains all the user verilog files. Here, 'source' is a file with all of the user's Verilog files(top.v, fsm1.v, fsm2.v, fsm3.v) and iv.v. iv.v is available in the example directory.

Precedence order for simulation mode options

The Verilog compiler determines the simulation mode of a module (compiled or interpreted) based on the invocation options `-comm <mod>', `-intm <mod>', `-comf <file>', `-intf <file>', `-comd <dir>', `-intd <dir>' and `-dsm <mode>'. The precedence order of these options are:

1. -comm <mod>, -intm <mod>

2. -comf <file>, -intf <file>

3. -comd <dir>, -intd <dir>

4. -dsm <mode>

For example, if the user types the following:

finvc -intf test.v -comm test

and the module `test' is defined in the file `test.v', then all modules in file

`test.v' will be interpreted except `test' which will be compiled.

NOTE: +VTCOMPRESS250 +VTVECTORVALUES will compress the size of the vt.dump file.Optimization is more in the case of designs with large number of vectors.

4)Run simulator as follows:

./runsim

runsim : script for running all finsim commands.

---------runsim contents--------------------------------------------------------------------------------

#!/bin/csh

# Usage: runsim <options>

# This is a sample script which runs the 3 steps required by the

# FinSim products:

# 1) finvc --- the Verilog compiler and code generator

# 2) finbuild --- the simulation builder

# 3) TOP.sim --- the simulator

# Different options for these 3 steps can be specified by using the

# variables FINVCOPT, FINBUILDOPT and FINSIMOPT below. For the compiler

# finvc, options can also be specified in the command file top.cf or

# passed directly in the command line of this script like this:

# runsim +notimingchecks -dsm int

# For a complete description of the available options please see the User

# Guide or run any of these commands with the option -help.

if (!($?FINTRONIC)) then

echo ""

echo " The environment variable FINTRONIC is not set. Please source the file"

echo " env/env.script in the installation directory and rerun this script"

echo ""

exit(1)

endif

set path = ($FINTRONIC/bin/$FIN_COMPILER $path)

# set the options for finvc

set FINVCOPT = "-cf top.cf -a -ol 9"

# set the options for finbuild

set FINBUILDOPT = "-verbose"

# set the options for TOP.sim

set FINSIMOPT = "-verbose"

# run the compiler finvc

finvc $FINVCOPT $*

if ($status != 0) then

echo ""

echo "***ERROR*** The compiler terminated abnormally. Please check the file finvc.log"

echo ""

exit(1)

endif

# run the simulation builder finbuild

finbuild $FINBUILDOPT

if ($status != 0) then

echo ""

echo "***ERROR*** The simulation builder terminated abnormally. Please check the files finbuild.log and compile.log"

echo ""

exit(1)

endif

# run the simulator TOP.sim

./TOP.sim $FINSIMOPT

if ($status != 0) then

echo ""

echo "***ERROR*** The simulation terminated abnormally. Please check the file

finsim.log"

echo ""

exit(1)

endif

echo ""

echo "The simulation has completed successfully"

echo ""

-------------------------------------------------------------------------------------------------------------

BATCH MODE

After you run your simulator and generate the signal files and/or trace files, you can use the Undertow Suite to run batch simulation. Batch simulation debugs your source code without tying up the simulator license.

To open the Undertow Suite in batch mode, the command lines are as follows:

ut -iv -f <source_code_file> -sigfile <signal_file> -tracefile <trace_file>

Here, source_code_file is the file thats lists all the source code files.

You can enter a single file that holds the names of other files (e.g., fsm.vc) or enter a list of design files. For example,

ut -iv -f fsm.vc -sigfile fsm.sigs -tracefile fsm.trace

ut -iv top.v fsm1.v fsm2.v fsm3.v -sigfile fsm.sigs

ut -iv top.vhd fsm1.vhd fsm2.vhd fsm3.vhd -sigfile fsm.sigs

To view just the waveform,

ut -v <signal_file>

For example,

ut -v vt.dump

INTERACTIVE MODE FOR FINSIM

In the interactive mode, you can run finsim using the Undertow suite.

To open the Undertow Suite in interactive mode, the command line is as follows:

ut -iv -finsim <simulator_executable> <simulator_options> -sigfile <signal_filename> -ivsimcmp "-f <file that lists all source code files>"

For example,

ut -iv -finsim TOP.sim -sigfile fsm.sigs -ivsimcmp "-f source"

INTERACTIVE MODE WITH TRACEFILE FOR FINSIM

To create trace dump files, you can invoke system tasks from within your Verilog source code. To enable or disable tracing of your complete design, invoke the $vtTrace system task, as follows:

$vtTracename(tracefilename)

$vtTrace(enableFlag)

where,

enableFlag is either

1: to enable tracing, or

0: to disable tracing

tracefilename is a string that specifies the name of the trace file.

To specify the name of the trace file, use the $vtTracename(tracefilename) system task before you invoke the $vtTrace system task in your source code.

To enable or disable tracing of specified sections of your design, invoke the $vtTrace systems task as follows:

$vtTrace(enableFlag, levels, root1, roo2,...);

where,

levels is an integer indicating how many levels to apply the enableFlag. A 0 for the levels argument signifies all levels.

root arguments indicate which root(s) to enable or disable tracing, for the specified number of levels.

You can invoke the $vtTrace system task any number of times with different parameters for each invocation.

The format to start Undertow in the interactive mode with a tracefile is as follows:

ut -iv -finsim <simulator_executable> <simulator_options> -sigfile <signal_filename> -tracefile <trace_filename> -ivsimcmp "-f <file that lists all source code

files>"

For example,

ut -iv -finsim TOP.sim -sigfile fsm.sigs -tracefile fsm.trace -ivsimcmp "-f source"

II) STEPS FOR SIMULATING USING VSIM (MODELTECH):

1)Source environment variables

For example,

./envsource

envsource has all the environment variables set up. You can change the paths accordingly.

------------envsource file contents---------------------------------------------------------------------

setenv PLIOBJS $UT_ROOT_DIR/PLI/vtpli_modtech.so

#setenv ModelTech <path where ModelTech has been installed>

setenv ModelTech /cad_tools/modeltech/5.8b/modeltech/bin/

--------------------------------------------------------------------------------------------------------------

vtpli_modtech.so is available in our PLI directory.

2) Add to source code close to top module

initial

begin

$vtDumpvars();

end

In this example, the above has been inserted in 'top.v' file.

3) Run simulator as follows:

./run_modeltech

run_modeltech : script for running all modeltech commands.

---------run_modeltech contents-----------------------------------------------------------------------

#!/bin/csh -f

if (-e work) then

rm -r -f work

endif

if (! -e work) then

vlib work #creates new design library work

endif

vlog -f source #compiles the verilog files into the work library

vsim -c -do 'run -all' top vtInteractive +VTCOMPRESS250 +VTVECTORVALUES

#vsim -c -do 'run -all' top vtInteractive

-------------------------------------------------------------------------------------------------------------

a) -f <file> : used to specify file that contains all the user verilog files. Here, 'source' is a file with all of the user's Verilog files(top.v, fsm1.v, fsm2.v, fsm3.v) and iv.v. iv.v is available in the example directory.

b) -c : run in command line mode.

c) -do 'run -all': to run until there are no more simulation events or until $finish is executed in the Verilog code.

d) top and vtInteractive are the top level modules in this example. The simulator vsim is invoked with the top level modules.

NOTE: +VTCOMPRESS250 +VTVECTORVALUES will compress the size of the vt.dump file. Optimization is more in the case of designs with large number of vectors.

BATCH MODE

To open the Undertow Suite in batch mode, the command lines are as follows:

ut -iv -f <source_code_file> -sigfile <signal_file> -tracefile <trace_file>

Here, source_code_file is the file thats lists all the source code files.

You can enter a single file that holds the names of other files (e.g., fsm.vc) or enter a list of design files. For example,

ut -iv -f fsm.vc -sigfile fsm.sigs -tracefile fsm.trace

ut -iv top.v fsm1.v fsm2.v fsm3.v -sigfile fsm.sigs

ut -iv top.vhd fsm1.vhd fsm2.vhd fsm3.vhd -sigfile fsm.sigs

To view just the waveform,

ut -v <signal_file>

For example,

ut -v vt.dump

INTERACTIVE MODE FOR VSIM (MODELTECH)

In the interactive mode, you can run vsim using the Undertow suite.

To open the Undertow Suite in interactive mode, the command line is as follows:

ut -iv -modeltech <simulator_executable_name> <top level module names> <simulator_options> -sigfile <signal_filename> -tracefile <trace_filename> -ivsimcmp "-f <file that lists all source code files>"

For example,

ut -iv -modeltech vsim top -sigfile fsm.sigs -tracefile fsm.trace -ivsimcmp "-f source"

III) STEPS FOR SIMULATING USING VCSI (SYNOPSYS):

1)Source environment variables

For example,

./envsource

envsource has all the environment variables set up. You can change the paths accordingly.

------------envsource file contents---------------------------------------------------------------------

setenv VCSI_HOME <path where VCSI is installed>

setenv DEFAULT_VCS_HOME <path where VCSI is installed>

setenv VCS_HOME <path where VCSI is installed>

setenv TMPDIR /tmp

setenv VCS_NETHOST vt1

setenv VCS_LTD_LICENSE 1

setenv VCS_cc cc

---------------------------------------------------------------------------------------------------------------

2)Add to source code close to top module

initial

begin

$vtDumpvars();

end

In this example, the above has been inserted in 'top.v' file.

3) To run simulator in batch mode, do as follows:

./run_vcsi_batch

run_vcsi_batch : script for running all VCSi commands

---------run_vcsi_batch contents------------------------------------------------------------------------------------------------------

#!/bin/csh -f

#vcsi <flags> -f source $UT_ROOT_DIR/PLI/vtplivcs.o -P $UT_ROOT_DIR/PLI/vt_vcs.tab

vcsi -Mupdate +rad +vcsd -f source $UT_ROOT_DIR/PLI/vtplivcs.o -P $UT_ROOT_DIR/PLI/vt_vcs.tab

./simv +VTCOMPRESS250 +VTVECTORVALUES

-----------------------------------------------------------------------------------------------------------------------------------------------

a) -f <file> : used to specify file that contains all the user verilog files. Here, 'source' is a file with all of the user's Verilog files (top.v, fsm1.v, fsm2.v, fsm3.v) and iv.v. iv.v is available in the example directory.

b) vtplivcs.o and vt_vcs.tab are available in our PLI directory. You need to link in the Veritools PLI routines when you compile your model with VCS. The Veritools PLI routines use these files to generate a VCS compiled model. vt_vcs.tab defines all Veritools user-defined PLI definitons.

c) -P: used to specify the PLI tab file.

NOTE: +VTCOMPRESS250 +VTVECTORVALUES will compress the size of the vt.dump file.Optimization is more in the case of designs with large number of vectors.

Compilation:

vcsi <flags> -f source $UT_ROOT_DIR/PLI/vtplivcs.o -P $UT_ROOT_DIR/PLI/vt_vcs.tab

Flags for increased performance:

+rad: Perform aggressive optimization for RTL or (non timing) gate level

+vcsd: Use more efficient Direct Kernel Interface for VirSim dumping

-Mupdate: Use incremental compile to only recompile modules that

functionally changed

+rad+1: Perform localized optimizations only

+nospecify: Ignore path delays and timing checks for functional gate simulations+notimingchecks: Ignore timing checks

+timopt: Perform agressive timing optimizations (for SDF gate simulations)

+nocelldefinepli+2: Do not dump or use PLI access from within library cells

+2state: Convert entire design (except certain constructs) to 2 states for more

speed/capacity

Flags that hinder performance:

+cli: Turn on interactive debug for the entire design

+cli+mod=#: Turn on interactive debug just for module mod

+acc: Obsolete flag to allow for global PLI access

-line: Allow line stepping in debugger

-00: Turn off optimizations

-I: Obsolete flag for interactive GUI debug. Instructs VCS to automatically include the +cli (command line interface), -P virsims.tab (default VirSim PLI table) and -lm (math library) options. This option is required to create VCD+ files like the -RI option. The virsims.tab file defines the VCD+ system tasks such as $vcdpluson. Unlike the -RI option, simulation with VirSim does not start after compilation but allows post-processing of the VCD+ file after simulation

-RI: Compile and run interactive debug with VirSim GUI

-PP: Allow VirSim vcd+ binary dumping for post-processing debug. Does the same thing as the -I option but minimizes detail of net data for faster post-processing

+race: Turn on race detection

+prof: Turn on VCS profiling

-gen_c: Force generation of C intermediate code instead of native object code

-P pli.tab which contains acc=rw, cbk:*: Globally turn on PLI access

+multisource_int_delays: Enables global PLI access visibility

+transport_int_delay: Enables global PLI access visibilty

-X*: version specific flags to work around specific bugs

Recommended Use:

vcsi -Mupdate +rad +vcsd -f source $UT_ROOT_DIR/PLI/vtplivcs.o -P $UT_ROOT_DIR/PLI/vt_vcs.tab

Simulation:

./simv +VTCOMPRESS250 +VTVECTORVALUES

4) To use interactive mode,

./run_vcsi_int

-------run_vcsi_int contents----------------------------------------------------------------------------------------------

#!/bin/csh -f

#vcsi <flags> -line -f source $UT_ROOT_DIR/PLI/vtplivcs.o -P $UT_ROOT_DIR/PLI/vt_vcs.tab

vcsi -Mupdate +cli +acc -lm -line -f source $UT_ROOT_DIR/PLI/vtplivcs.o -P $UT_ROOT_DIR/PLI/vt_vcs.tab

-------------------------------------------------------------------------------------------------------------------------------

The -line option must be given if you want to run Undertow Suite in interactive mode. The -line option is not required for running VCS in batch mode.

Using 64-bit Solaris version of Undertow with 64-bit VCS:

ELF class error:

This says that you are using incompatible simulators and PLIs/UT binaries. Either simulator is 64-bit and UT/PLI is 32-bit or vice-versa.

I) On the 64-bit machine using the 64-bit install, please make sure you set the UT_ROOT_DIR environment variable to the

64-bit Solaris UT installation directory in your ".cshrc" file and do a source ~/.cshrc before you use "ut".

setenv UT_ROOT_DIR <path_to_64bit_UT_installation_dir>

This must be given in ~/.cshrc

%source ~/.cshrc

Verify the above and make sure that UT_ROOT_DIR points to a 64 bit ut install using:

%echo $UT_ROOT_DIR //64-bit install

%which ut //64-bit install

II) Please use the "-full64" option with vcs or vcsi during compilation on the 64-bit Solaris machine to generate the 64-bit simv executable.

VCS provides two types of compilation processes that take advantage of the additional memory capacity of 64-bit machines:

1) 64-32-Bit Cross-Compilation: In this process you use the -comp64 option to compile a design on a 64-bit machine; then run simv on either a 32-bit or 64-bit machine.

2) Full 64-Bit Compilation: In this process, you use the -full64 option to compile a design on a 64-bit machine; then run simv on a 64-bit machine.

Use the "-full64" option with vcs or vcsi during compilation on the 64-bit Solaris machine to generate the 64-bit simv executable.

For example:

Compilation, use:

vcsi -full64 +cli+acc+4-Mupdate -f source $UT_ROOT_DIR/PLI/vtplivcs.o -P $UT_ROOT_DIR/PLI/vt_vcs.tab -lm

For simulation, please use:

./simv +VTCOMPRESS250 +VTVECTORVALUES

NOTE: +VTCOMPRESS250 +VTVECTORVALUES will compress the size of the vt.dump file. Optimization is more in the case of designs with large number of vectors.

Alternatively, if you want to use 32-bit compilation, make sure you use our 32-bit Solaris PLI instead. The -full64 option should resolve the ELF class error issue. IF NOT, set UT_ROOT_DIR to the 32 bit install and see if that works instead.

III) VCS cc or gcc compiler:

Please make sure that the compiler you use for VCS (cc/gcc) is the 64-bit version. Check the path for cc/gcc. This has to point to the 64-bit Solaris executable. So check all the files that you "source" for the corresponding PATHS.

IV) You MUST have write permissions for the directory from which you open UT as it needs to create some ut.dot and/or

vt.dump.open files to be able to open UT using the following:

%ut -v vt.dump

%ut -iv -f source -sigfile vt.dump

Check the write permissions for your current design directory.

BATCH MODE

To open the Undertow Suite in batch mode, the command lines are as follows:

ut -iv -f <source_code_file> -sigfile <signal_file> -tracefile <trace_file>

Here, source_code_file is the file thats lists all the source code files.

You can enter a single file that holds the names of other files (e.g., fsm.vc) or enter a list of design files. For example,

ut -iv -f fsm.vc -sigfile fsm.sigs -tracefile fsm.trace

ut -iv top.v fsm1.v fsm2.v fsm3.v -sigfile fsm.sigs

ut -iv top.vhd fsm1.vhd fsm2.vhd fsm3.vhd -sigfile fsm.sigs

To view just the waveform,

ut -v <signal_file>

For example,

ut -v vt.dump

INTERACTIVE MODE FOR VCS

In the interactive mode, you can run vcs using the Undertow suite.

To open the Undertow Suite in interactive mode, the command line is as follows:

ut -iv -vcs <vcs_simulator_executable> <simulator_options> -sigfile <signal_filename> -tracefile <tracefile> -ivsimcmp "-f <file that lists all source code file names>"

For example,

ut -iv -vcs simv -sigfile fsm.sigs -tracefile fsm.trace -ivsimcmp "-f source"

CREATING TRACEFILE

To create trace dump files, you can invoke system tasks from within your Verilog source code. To enable or disable tracing of your complete design, invoke the $vtTrace system task, as follows:

$vtTracename(tracefilename)

$vtTrace(enableFlag)

where,

enableFlag is either

1: to enable tracing, or

0: to disable tracing

tracefilename is a string that specifies the name of the trace file.

To specify the name of the trace file, use the $vtTracename(tracefilename) system task before you invoke the $vtTrace system task in your source code.

To enable or disable tracing of specified sections of your design, invoke the $vtTrace systems task as follows:

$vtTrace(enableFlag, levels, root1, roo2,...);

where,

levels is an integer indicating how many levels to apply the enableFlag. A 0 for the levels argument signifies all levels.

root arguments indicate which root(s) to enable or disable tracing, for the specified number of levels.

You can invoke the $vtTrace system task any number of times with different parameters for each invocation.

IV) STEPS FOR SIMULATING USING NCSIM (CADENCE):

1)Source environment variables

For example,

./envsource

envsource has all the environment variables set up. You can change the paths accordingly. Make sure that the $CDS_INST_DIR is defined for your Cadence installation directory.

--------------envsource file contents-------------------------------------------------------------------

#setenv CDS_INST_DIR <cadence installation directory>

setenv CDS_INST_DIR /cad_tools/LDV5.1

setenv ittsimUndertowSeDir $CDS_INST_DIR/tools/dfII/local/undertow

setenv LD_LIBRARY_PATH /usr/lib:/usr/openwin/lib:$CDS_INST_DIR/tools/dfII/lib:$CDS_INST_DIR/tools/inca/lib:$CDS_INST_DIR/tools/lib:$CDS_INST_DIR/tools/lib:$CDS_INST_DIR/tools/verilog/lib:/usr/dt/lib:/usr/lib/x11:/usr/ucblib:/usr20/dt_cde/lib:/usr/local/lib/gcc-lib:/usr/local/lib:{SILOS}/bin:$UT_ROOT_DIR/PLI

-------------------------------------------------------------------------------------------------------------------

Make sure LD_LIBRARY_PATH has $UT_ROOT_DIR/PLI/ specified in the path.

NOTE:

For UNDERTOW versions 2003.1.8 and up:

Use the correct PLI according according to the simulator type and version. $UT_ROOT_DIR/PLI has the following .so files:

libpli.so.nc_verilog: For latest CADENCE LDV versions 4.1, 5.1, 5.2 and up

libpli.so.old_nc_verilog: For earlier CADENCE LDV versions

Make sure you do the following:

%cd $UT_ROOT_DIR/PLI/

%cp <the appropriate libpli.so.#####> libpli.so

For UNDERTOW versions 2003.1.7 and below:

For latest CADENCE LDV versions 4.1, 5.1, 5.2 and up:

Make sure you do the following:

%cd $UT_ROOT_DIR/PLI/

%mv libpli.so libpli.so.old

%cp libplivpi.so libpli.so

For earlier CADENCE LDV versions, libpli.so is used by default.

2)Add to source code close to top module

initial

begin

$vtDumpvars();

end

In this example, the above has been inserted in 'top.v' file.

3) If you are simulating your design for the first time, follow these steps:

a) Run "ncprep"

>ncprep -f source

-f <file> : used to specify file that contains all the user verilog files. Here, 'source' is a file with all of the user's Verilog files(top.v, fsm1.v, fsm2.v, fsm3.v) and iv.v. iv.v is available in the example directory.

Note that ncprep will generate the following files and directories.

cds.lib
hdl.vars
INCA_LIB

ncvlog.args
ncelab.args

ncsim.args

b) Run "ncvlog"

>ncvlog -f ncvlog.args

c) Add the following line into file "ncleab.args"

-ACCESS +RCW

d) Run "ncelab"

>ncelab -f ncelab.args

e) Run "ncsim"

>ncsim -f ncsim.args

4)You can then run the simulator again as follows:

./run_ncsim

run_ncsim : script for running all ncsim commands.

---------run_ncsim contents----------------------------------------------------------------------------

#!/bin/csh -f

ncprep -f source +overwrite

# Run the NC-Verilog parser (compile the source)

ncvlog -f ncvlog.args

if ($status != 0) then

exit

endif

# Run the NC-Verilog elaborator (build the design hierarchy)

ncelab -f ncelab.args -ACCESS +RCW

if ($status != 0) then

exit

endif

# Run the NC-Verilog simulator (simulate the design)

ncsim -f ncsim.args

-------------------------------------------------------------------------------------------------------------

The +overwrite option is used to overwrite the files and directories created earlier by ncprep.

The -ACCESS +RCW turns on the read, connectivity and write access visibility.

BATCH MODE

To open the Undertow Suite in batch mode, the command lines are as follows:

ut -iv -f <source_code_file> -sigfile <signal_file> -tracefile <trace_file>

Here, source_code_file is the file thats lists all the source code files.

You can enter a single file that holds the names of other files (e.g., fsm.vc) or enter a list of design files. For example,

ut -iv -f fsm.vc -sigfile fsm.sigs -tracefile fsm.trace

ut -iv top.v fsm1.v fsm2.v fsm3.v -sigfile fsm.sigs

ut -iv top.vhd fsm1.vhd fsm2.vhd fsm3.vhd -sigfile fsm.sigs

To view just the waveform,

ut -v <signal_file>

For example,

ut -v vt.dump

INTERACTIVE MODE FOR NCSIM

In the interactive mode, you can run ncsim using the Undertow suite.

To open the Undertow Suite in interactive mode, the command line is as follows:

ut -iv -nc ncsim "-f ncsim.args" -sigfile <signal_filename> -tracefile <trace_filename> -ivsimcmp "-f <file that lists all source code file names>"

For example,

ut -iv -nc ncsim "-f ncsim.args" -sigfile fsm.sigs -tracefile fsm.trace -ivsimcmp "-f source"

ut -iv -nc ncsim worklib.top:v -sigfile fsm.sigs -tracefile fsm.trace -ivsimcmp "-f source"

V) STEPS FOR SIMULATING USING NC Verilog XL (CADENCE)

1)Source environment variables

For example,

./envsource

envsource has all the environment variables set up. You can change the paths accordingly. Make sure that the $CDS_INST_DIR is defined for your Cadence installation directory.

--------------envsource file contents-------------------------------------------------------------------

#setenv CDS_INST_DIR <cadence installation directory>

setenv CDS_INST_DIR /cad_tools/LDV5.1

setenv ittsimUndertowSeDir $CDS_INST_DIR/tools/dfII/local/undertow

-------------------------------------------------------------------------------------------------------------------

Make sure LD_LIBRARY_PATH has $UT_ROOT_DIR/PLI/ specified in the path.

NOTE:

For UNDERTOW versions 2003.1.8 and up:

Use the correct PLI according according to the simulator type and version. $UT_ROOT_DIR/PLI has the following .so files:

libpli.so.nc_verilog: For latest CADENCE LDV versions 4.1, 5.1, 5.2 and up

libpli.so.old_nc_verilog: For earlier CADENCE LDV versions

Make sure you do the following:

%cd $UT_ROOT_DIR/PLI/

%cp <the appropriate libpli.so.#####> libpli.so

For UNDERTOW versions 2003.1.7 and below:

For latest CADENCE LDV versions 4.1, 5.1, 5.2 and up:

Make sure you do the following:

%cd $UT_ROOT_DIR/PLI/

%mv libpli.so libpli.so.old

%cp libplivpi.so libpli.so

For earlier CADENCE LDV versions, libpli.so is used by default.

2)Add to source code close to top module

initial

begin

$vtDumpvars();

end

In this example, the above has been inserted in 'top.v' file.

3) Run simulator as follows:

./run_ncxlmode

run_ncxlmode : script for running ncxlmode.

---------run_ncxlmode contents-----------------------------------------------------------------------

ncxlmode -f source +ncelabargs+"-access +RWC"

------------------------------------------------------------------------------------------------------------

The -access +RWC turns on the read, write and connectivity access visibility.

BATCH MODE

To open the Undertow Suite in batch mode, the command lines are as follows:

ut -iv -f <source_code_file> -sigfile <signal_file> -tracefile <trace_file>

Here, source_code_file is the file thats lists all the source code files.

You can enter a single file that holds the names of other files (e.g., fsm.vc) or enter a list of design files. For example,

ut -iv -f fsm.vc -sigfile fsm.sigs -tracefile fsm.trace

ut -iv top.v fsm1.v fsm2.v fsm3.v -sigfile fsm.sigs

ut -iv top.vhd fsm1.vhd fsm2.vhd fsm3.vhd -sigfile fsm.sigs

To view just the waveform,

ut -v <signal_file>

For example,

ut -v vt.dump

INTERACTIVE MODE FOR NC VERILOG-XL

In the interactive mode, you can run ncxlmode using the Undertow suite.

To open the Undertow Suite in interactive mode, the command line is as follows:

ut -iv -ncxlmode ncxlmode -f <file that lists all source code filenames> -sigfile <signal_filename> -tracefile <trace_filename>

For example,

ut -iv -ncxlmode ncxlmode -f source -sigfile fsm.sigs -tracefile fsm.trace

VI) STEPS FOR SIMULATING USING NC VERILOG (CADENCE)

1)Source environment variables

For example,

./envsource

envsource has all the environment variables set up. You can change the paths accordingly. Make sure that the $CDS_INST_DIR is defined for your Cadence installation directory.

--------------envsource file contents-------------------------------------------------------------------

#setenv CDS_INST_DIR <cadence installation directory>

setenv CDS_INST_DIR /cad_tools/LDV5.1

setenv ittsimUndertowSeDir $CDS_INST_DIR/tools/dfII/local/undertow

-------------------------------------------------------------------------------------------------------------------

Make sure LD_LIBRARY_PATH has $UT_ROOT_DIR/PLI/ specified in the path.

NOTE:

For UNDERTOW versions 2003.1.8 and up:

Use the correct PLI according according to the simulator type and version. $UT_ROOT_DIR/PLI has the following .so files:

libpli.so.nc_verilog: For latest CADENCE LDV versions 4.1, 5.1, 5.2 and up

libpli.so.old_nc_verilog: For earlier CADENCE LDV versions

Make sure you do the following:

%cd $UT_ROOT_DIR/PLI/

%cp <the appropriate libpli.so.#####> libpli.so

For UNDERTOW versions 2003.1.7 and below:

For latest CADENCE LDV versions 4.1, 5.1, 5.2 and up:

Make sure you do the following:

%cd $UT_ROOT_DIR/PLI/

%mv libpli.so libpli.so.old

%cp libplivpi.so libpli.so

For earlier CADENCE LDV versions, libpli.so is used by default.

2)Add to source code close to top module

initial

begin

$vtDumpvars();

end

In this example, the above has been inserted in 'top.v' file.

3) Run simulator as follows:

./run_ncverilog

run_ncverilog : script for running ncverilog.

---------run_ncverilog contents-----------------------------------------------------------------------

ncverilog -f source +ncelabargs+"-access +RWC"

------------------------------------------------------------------------------------------------------------

The -access +RWC turns on the read, write and connectivity access visibility.

BATCH MODE

To open the Undertow Suite in batch mode, the command lines are as follows:

ut -iv -f <source_code_file> -sigfile <signal_file> -tracefile <trace_file>

Here, source_code_file is the file thats lists all the source code files.

You can enter a single file that holds the names of other files (e.g., fsm.vc) or enter a list of design files. For example,

ut -iv -f fsm.vc -sigfile fsm.sigs -tracefile fsm.trace

ut -iv top.v fsm1.v fsm2.v fsm3.v -sigfile fsm.sigs

ut -iv top.vhd fsm1.vhd fsm2.vhd fsm3.vhd -sigfile fsm.sigs

To view just the waveform,

ut -v <signal_file>

For example,

ut -v vt.dump

INTERACTIVE MODE FOR NC VERILOG

In the interactive mode, you can run ncverilog using the Undertow suite.

To open the Undertow Suite in interactive mode, the command line is as follows:

ut -iv -nc ncverilog “-f <file that lists all source code filenames>” -sigfile <signal_filename> -tracefile <trace_filename>

For example,

ut -iv -nc ncverilog “-f source” -sigfile fsm.sigs -tracefile fsm.trace

VII) STEPS FOR SIMULATING USING VERILOG XL (CADENCE)

1)Source environment variables

For example,

./envsource

envsource has all the environment variables set up. You can change the paths accordingly. Make sure that the $CDS_INST_DIR is defined for your Cadence installation directory.

--------------envsource file contents-------------------------------------------------------------------

#setenv CDS_INST_DIR <cadence installation directory>

setenv CDS_INST_DIR /cad_tools/LDV5.1

setenv ittsimUndertowSeDir $CDS_INST_DIR/tools/dfII/local/undertow

-------------------------------------------------------------------------------------------------------------------

Make sure LD_LIBRARY_PATH has $UT_ROOT_DIR/PLI/ specified in the path.

NOTE:

For UNDERTOW versions 2003.1.8 and up:

Use the correct PLI according according to the simulator type and version. $UT_ROOT_DIR/PLI has the following .so file:

libpli.so.verilog_xl

Make sure you do the following:

%cd $UT_ROOT_DIR/PLI/

%cp libpli.so.verilog_xl libpli.so

For UNDERTOW versions 2003.1.7 and below:

For latest CADENCE LDV versions 4.1, 5.1, 5.2 and up:

Make sure you do the following:

%cd $UT_ROOT_DIR/PLI/

%mv libpli.so libpli.so.old

%cp libplivpi.so libpli.so

For earlier CADENCE LDV versions, libpli.so is used by default.

2)Add to source code close to top module

initial

begin

$vtDumpvars();

end

In this example, the above has been inserted in 'top.v' file.

3) Run simulator as follows:

./run_verilog

run_verilog : script for running verilog.

---------run_verilog contents-----------------------------------------------------------------------

verilog -f source

#source is the file that contains a list of all source code verilog files

------------------------------------------------------------------------------------------------------------

BATCH MODE

To open the Undertow Suite in batch mode, the command lines are as follows:

ut -iv -f <source_code_file> -sigfile <signal_file> -tracefile <trace_file>

Here, source_code_file is the file thats lists all the source code files.

You can enter a single file that holds the names of other files (e.g., fsm.vc) or enter a list of design files. For example,

ut -iv -f fsm.vc -sigfile fsm.sigs -tracefile fsm.trace

ut -iv top.v fsm1.v fsm2.v fsm3.v -sigfile fsm.sigs

ut -iv top.vhd fsm1.vhd fsm2.vhd fsm3.vhd -sigfile fsm.sigs

To view just the waveform,

ut -v <signal_file>

For example,

ut -v vt.dump

INTERACTIVE MODE FOR VERILOG-XL

In the interactive mode, you can run verilog using the Undertow suite.

To open the Undertow Suite in interactive mode, the command line is as follows:

ut -iv -xl verilog -f <file that lists all source code filenames> -sigfile <signal_filename> -tracefile <trace_filename>

For example,

ut -iv -xl verilog -f source -sigfile fsm.sigs -tracefile fsm.trace