Veritools HDL Debugging Solutions
 

veritools announces

TOPIC: VeritoolsDesigner

Veritools Inc., the leading provider of electronic design, debugging and verification tools, today announced its new product VeritoolsDesigner. VeritoolsDesigner, a source code debugging environment for Verilog, now includes fully elaborated RTL schematics for VHDL and full support for SystemVerilog Assertions. This all-in-one debugging product provides designers with synchronous windows for viewing their design's source code, waveforms, RTL/Gate schematics and state diagrams.

The VeritoolsDesigner includes the HDL Analyzer, a complete RTL synthesizer for schematic generation. Veritools' data formats provide almost instantaneous schematic and waveform load/display, in addition to file compression of up to 1,300 times. Veritools supports almost all digital and analog simulators on a variety of platforms.

"As first-silicon-tapeout success has significantly declined in the last several years, designers are now focusing more time on functional verification and functional verification coverage. Veritools' new enhancements reconfirm our commitment to adding features that can significantly improve productivity to this verification environment," said Bob Schopmeyer, president of Veritools, Inc.

VeritoolsDesigner is a "no cost" upgrade for current Undertow Suite customers with active maintenance contracts.

New features include:

  • New Easy-to-use User Interface
  • Source Code Debugging for Verilog, VHDL, Mixed Mode and now SystemVerilog including:
    • Complete RTL Synthesizer using HDL Analyzer
    • RTL & Gate Schematics
  • State Diagrams
  • PLI provides faster simulation with file compression up to 1,300x
  • Gate Power Analysis
  • Full Support for PSL Assertions including evaluations and analysis coverage
  • PERL/TK and TCL/TK Scripting

Veritools Inc., the leading provider of electronic design, debugging and verification tools, today announced its new VeritoolsDesigner release. VeritoolsDesigner, a source code debugging environment for Verilog, now includes fully elaborated RTL schematics for VHDL and full support for SystemVerilog Assertions. This all-in-one debugging product provides designers with synchronous windows for viewing their design's source code, waveforms, RTL/Gate schematics and state diagrams. The VeritoolsDesigner iincludes the HDL Analyzer, a complete RTL synthesizer for schematic generation. Veritools' data formats provide almost instantaneous schematic and waveform load/display, in addition to file compression of up to 1,300 times. Veritools supports almost all digital and analog simulators on a variety of platforms.

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