veritools announces

TOPIC: VeritoolsVerifyer

VeritoolsVerifyer analyzes the user's SystemVerilog assertions and graphically displays evaluation results. The color-coded results of the evaluation are shown in the user's design hierarchy and also in the integrated waveform window. The user can select any unique assertion evaluation and display the assertion timing along with the signal components from that assertion evaluation. Unique assertion threads are also shown on the assertion timing waveform. Any unique execution thread can be selected and displayed along with all of the local variables for that thread.

On the analysis window, VeritoolsVerifyer displays the portion of the assertion that passes and the portion that fails. This allows the user to instantly see which term or signal caused the assertions to fail. The user then uses the "What If" edit window to modify portions of the failed assertion and then view the new evaluation results instantly. Assertions can be modified and re-evaluated any number of times in just a few seconds. With a "simulator only" approach these same operations take hours. With the next generation of ASICs, the number of lines of assertion code will approach 100,000 lines, and this savings in time will be significant. "This will spell the difference between completing verification or going to tape-out in the middle of the verification process, before the verification process is even finished," says Bob Schopmeyer, President of Veritools, Inc.

VeritoolsVerifyer also provides a SystemVerilog assertion coverage generator and accumulator. By automatically generating coverage metrics the user can accumulate results over a number of evaluation runs. In order to debug an assertion, the user can go instantly from any failed assertion to the waveform results for that assertion .

Assertion evaluation results from a variety of simulators can easily be correlated to the VeritoolsVerifyer evalution results.

The VeritoolsVerifyer is integrated with VeritoolsDesigner, the industry's only affordably priced RTL/Gate source code debugging environment for Verilog, VHDL and SystemVerilog designs, supporting not only digital but mixed digital/analog designs.

Veritools Inc., the leading provider of electronic design, debugging and verification tools, today announced its new VeritoolsDesigner release. VeritoolsDesigner, a source code debugging environment for Verilog, now includes fully elaborated RTL schematics for VHDL and full support for SystemVerilog Assertions. This all-in-one debugging product provides designers with synchronous windows for viewing their design's source code, waveforms, RTL/Gate schematics and state diagrams. The VeritoolsDesigner iincludes the HDL Analyzer, a complete RTL synthesizer for schematic generation. Veritools' data formats provide almost instantaneous schematic and waveform load/display, in addition to file compression of up to 1,300 times. Veritools supports almost all digital and analog simulators on a variety of platforms.