White Paper

TOPIC: Why use SystemVerilog Assertions?

The constant increase in design size and complexity has resulted in significantly more bugs and in substantially more time spent in the verification process. Current estimates show that many of today's designs require 70% or greater time for the verification process, a process that is now unfortunately resulting in a lower and lower percentage of first silicon success. Respinning a mask because of undetected functional bugs results in significant additional costs, and can cause substantial delays in the FPGA or ASIC project. Most companies today also want to maintain legacy designs while at the same time they want to incrementally transition over to newer and more powerful verification languages and methodologies. Most companies want to add in new technologies with the least disruption to their current processes and design practices.

Because new technology, languages and methodologies frequently require a substantial learning curve, companies would like to adopt new technology with the least amount of effort and pain as is possible. Most companies would prefer to keep their ability to work with existing methodologies while at the same time also allowing them to use the more powerful verification languages such as SystemVerilog and other methodologies. This clearly requires an incremental approach when making the transition to new technologies.

While almost all of the major electronic companies are today beginning to investigate how they can take advantage of SystemVerilog assertions to provide a more productive environment for verifying designs, many of the most forward looking companies have already adopted extensive use of SystemVerilog Assertions into their verification process with great success. These companies not only are achieving a much higher rate of first silicon success, but now believe they could not get functioning ASICs without the extensive use of assertion code. Even today, many of the ASICs they are working on require over 100,000 lines of assertion code. This extensive use of assertions has however resulted in the several design issues:

Because new technology, languages and methodologies frequently require a substantial learning curve, companies would like to adopt new technology with the least amount of effort and pain as is possible. Most companies would prefer to keep their ability to work with existing methodologies while at the same time also allowing them to use the more powerful verification languages such as SystemVerilog and other methodologies. This clearly requires an incremental approach when making the transition to new technologies.

While almost all of the major electronic companies are today beginning to investigate how they can take advantage of SystemVerilog assertions to provide a more productive environment for verifying designs, many of the most forward looking companies have already adopted extensive use of SystemVerilog Assertions into their verification process with great success. These companies not only are achieving a much higher rate of first silicon success, but now believe they could not get functioning ASICs without the extensive use of assertion code. Even today, many of the ASICs they are working on today require over 100,000 lines of assertion code. This extensive use of assertions has, however, resulted in the several design issues:

1. How to mange the complexity of this much code?
2. How to see where these assertions are actually located in the design?
3. How to debug large numbers of assertions quickly with tools that provide high visibility into exactly what these assertions are actually doing? (This problem is compounded by the fact that any assertion can be executed at any clock, and even beyond this, can have any number of separate unique execution threads, with each thread having its own unique local variables.)
4. How to quickly determine exactly what the functional coverage is for the assertion tests that are run?
5. How to determine where are the ASIC functions have not been fully tested?

VeritoolsVerifyer addresses these issues in the following ways: This current tool set includes two classes of tools that are integrated into a single tool set. A powerful source code-debugging environment called VeritoolsDesigner has been integrated with VeritoolsVerifyer, a stand-alone tool for the evaluation and analysis of SystemVerilog Assertions.

VeritoolsDesigner

VeritoolsDesigner is a complete source code-debugging environment with source code debugging windows, waveform viewing windows, stated diagram display windows, and schematic windows for RTL or Gate Designs. All windows are time synchronized to any simulation time point. This tool uses a highly optimized file format for simulation result data that is created from PLI, VPI and VHPI directly with any simulator on the market that uses these standards. This includes virtually all of the simulators on the market today. Over 6000 seats of this software are now found in the electronics industry today in over 350 companies in 44 countries.

VeritoolsVerifyer

The VeritoolsVerifyer is a complete tool set to provide support for verification using SystemVerilog Assertions, and includes a powerful stand-alone SystemVerilog Assertions evaluator. This tool can not only evaluate your SVAssertions an unlimited number of times without requiring any resimulation, but will also automatically generate complete SVAssertion coverage information.

Display of graphical data and waveforms using VeritoolsVerifyer

The users SystemVerilog Assertions are displayed directly in the users design hierarchy so users can see exactly where their assertion code is located. After evaluation of SystemVerilog assertions, the results are color coded in the design hierarchy to indicate the out come of the assertion evaluation, yellow indicates vacuously true, green, indicates the assertion was true or passed, and red indicates an assertion that has a fail execution cycle. Users can quickly see exactly where their assertions are located, and can quickly see which ones are failing. Not only is a result waveform available for every assertion, but users can also display the assertion timing result along with all of the signal components that were part of this assertion evaluation. Users can even quickly see exactly where the unique execution threads are for each unique assertion execution, and see what are the values of the local variables for this unique assertion thread.

"What if" Window

VeritoolsVerifyer also includes a "What If" window that allow users to edit any assertion and then to see the evaluation result of this modified assertion code, in most cases in just fractions of a second.

Open standards

These tools support Verilog, Verilog 2001, VHDL and SystemVerilog languages, and support all of the common simulators in use today, including NCSim from Cadence, Modeltech from Mentor and VCS and VCS MX from Synopsys, and SuperFinSim from Fintronics. In addition these tools support virtually all of the interface standards, including PLI, VPI, VHPI for interfacing with these simulators, and support file formats such as VPD, VCD, eVCD, .wlf, in addition to all of the analog standard formats such as TR0, AC Sweep, DC Sweep, ft0, CSDF, PSF binary, .out, .dou, and .cou.

The VeritoolsDesigner can work with any or even all of these simulators, in either interactive or a batch mode to provide universal support for all of the currently available simulators and file formats used in the EDA industry today.

Allows Incremental use of new standards

Users of Verilog, or VHDL can add in and start using SystemVerilog Assertions today in an incremental approach, without changing any part of their current design processes. Since SystemVerilog Assertions can "bind" into existing designs from modules outside of these designs, no change is required in order to start using SystemVerilog Assertions with today's designs. Users do not even have to upgrade their Verilog or VHDL simulators if they do not want to a simulator that supports SystemVerilog. They can use their current Verilog or VHDL simulators and use the VeritoolsVerifyer to do the evaluation of the SystemVerilog assertions separately from the design simulation process. Seamless integration with today's design methodologies These tools can be used with today's current design practices and will work seamlessly with any of the design languages and methodologies companies are using today. The ultimate result is this tool allows users to take advantage of the new SystemVerilog Assertion standards in an incremental approach in order to achieve a higher level of verification. The end result will be a significantly higher percentage of first silicon success.

About Veritools

Veritools, Inc., is one of the leading providers of electronic design, debugging and verification tools. Founded in 1992, Veritools now provides its verification products to over 4,000 engineers in over 400 companies throughout the world. Headquartered in Palo Alto, California, Veritools is dedicated to making the fastest design, debugging and verification tools for designers who use Verilog, VHDL, Mixed Mode, and SystemVerilog. For more information please stop by our booth at the Design Automation Conference Booth #3651, or visit our web site at www.veritools.com