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TOPIC: Coverage Driven Verification?

Today's ASIC and FPGA designers are perhaps facing their biggest challenge to date in the electronics industry. How to design and test the new generation of ASICs and FPGAs, as they get bigger and more complex? Because the verification process is taking so long, many companies elect to go to tape out prior to the verification even being complete, in order to meet aggressive schedules and as a result the rate of first silicon success has declined markedly at these companies. This not only costs millions of dollars in having to re-spin the masks, but means that these designs are late to market or in many cases miss their market windows altogether. Because of this, many designers have focused on Coverage Driven Verification using SystemVerilog Assertions to solve this problem for a number of reasons.

SystemVerilog Assertions can be used with today's ASIC design processes and languages, including Verilog, VHDL and SystemVerilog. Since SystemVerilog includes the concept of "bind", users are not forced to have to move from their current process to an entirely new design language to take advantage of SystemVerilog Assertions for verification of their designs. Because SystemVerilog Assertions includes the concept from day one of test coverage, this one language is ideal for both functional verification and functional verification coverage. With SystemVerilog Assertions, not only can the verification process get to a much higher level of completeness in the same amount of time, but users can see immediately exactly how far they have come in the verification process.

Veritools has focused on SystemVerilog Assertion tools, and has integrated together a complete SystemVerilog Assertion evaluation and analysis environment with a complete Source Code debugging environment for Verilog., VHDL and SystemVerilog.

Veritools in the past has focused on tools for both analog and digital design, debugging and verification. Our waveform tools are currently one of the most if not the most widely used tools on the market, with over 6000 designers having used these tools. Veritools is now focused more and more verification and in improving the rate of first silicon success at electronic companies doing ASICs. This one issue has now become the number one issue in the electronics industry. The problem we are trying to solve: The rate of first silicon success has gone from 90% 5 years ago to about 55-60 % today, even with a much larger effort devoted to the verification process.

Verification is now currently taking 70-80% of the time for the entire design process and because of the difficulty in completing this effort, it is leaving a ever increasing number of design errors which cause an increasing failure rate of first silicon. The verification process today is not only taking too long but is also not getting done to a sufficient degree to ensure a high rate of first silicon success. And the biggest issue is that even as the rate of first silicon success has fallen to an already low number, as designs get larger and larger the rate of first silicon success is expected to declining even more with every new future ASIC design

How do we expect to help with the verification process?

Veritools is now offering the industries most powerful suite of tools to do functional design verification using SystemVerilog Assertions. These tools include:

  • A SystemVerilog parser, currently the most complete on the market with a SystemVerilog Assertion compiler
These tools provide a complete stand alone SVAssertion evaluator

Advantages of stand alone SystemVerilog Assertion evaluation:

  • The SVAssertion evaluation can be done very quickly in most cases, generally in seconds.
  • The SystemVerilog Assertion Evaluation can be run an unlimited number of times without having to resimulate.
  • A SystemVerilog Analysis windowtakes advantages of the SVEvaluation to show designers what part of their assertion expression is passing and what part of the assertion is failing. provided to users can quickly see what part of their assertion expression is passing and what part of the assertion is failing.
  • A "What If" window is also provided so users can create a new assertion or modify any assertion that failed and can see instantly if this new assertion will pass. This edit assertion and rerun assertion evaluation can be run any number of times, with each iteration taking generally just seconds.

Issues in using Assertions for design verification:

    Why is it hard for simulators to evaluate assertion code?
  • Verilog and VHDL designs elements have two important characteristics affecting their use and simulation speed:
    1. Declaration
    2. Instantiation
  • Assertions are much more powerful because assertions have three important characteristics.
    1. Declaration
    2. Instantiation
    3. add Execution each and every SVAssertion has to be evaluated each clock cycle, and each assertion can be executed on every clock cycle.

Because of this assertions generally will have a very deleterious effect on simulation speed, in some cases a significant slow down will occur in the in simulation speed when the SystemVerilog assertion code is evaluated along with the design. Users can experience a 2, 5 X or even many users will have a 100 X slow down depending on the amount of assertion code they are attempting to evaluate along with their design code.

Speed advantages using the Veritools assertions evaluation to evaluate assertions:

Because the VeritoolsVerifyer includes a stand alone assertion evaluator, the users SVAssertion evaluations can be done completely in a simulation post process,eliminating the degradation of simulator performance when analyzing SVAssertions during the design simulation.

SVAssertion analysis can even be done much faster than when using a simulator only approach. Many SVAssertion evaluation cycles can be run in a short time. Simulators will require much longer times due to the fact they are regenerating 99.9% redundant data, data they have already generated previously.

Making it easier to debug SystemVerilog assertion code:

Not only are the assertions the users has added to their design displayed in their design hierarchy, but the assertion results are also displayed with the result of each assertion evaluation color coded; Yellow indicates that the assertion evaluation was all Vacuously True, Green indicates that the assertion had at least one Passed cycle, and had no failed cycles, and Red indicates that the assertion evaluation had at least one failed execution cycle.

The actual outcome from each assertion evaluation is presented to the user in easy to use waveform results. Users no longer have to use text files and/or print statements to view and debug their assertions. Both the result of the evaluation is displayed along with the assertion timing result for each user selected assertion evaluation cycle. In addition the signals that made up the assertion evaluation can be displayed.

These tools also allow the users to see exactly where unique assertion threads are located in any assertion timing result, and to even see the values and waveforms for all local variables in any unique assertion execution thread. No other software even comes close to this capability.

As users add more and more assertion code to their ASIC and FPGA designs in order to get these designs to work, using these type of tools may well spell the difference to actually being able to complete the verification process, or to having to go to tape out long before the verification process is any where near completed due to schedule pressures. When these not thoroughly ASICs fail not only will the re-mask charges cost millions, but the entire product viability may thrown into jeopardy due to being late to the market window.

What customers have said at design conferences:

One customer from the one of world leading maker of network routers stated that: "We are expecting to have over 100,000 lines of assertion code per ASIC in their new generation of designs." They further said that: "We could never get our chips to even work without this sort of verification effort." "But our current process is taking too long and impacting our simulation speeds significantly." One of our biggest issues is that we currently can not see where in the design these assertions are located or even exactly what these assertions are doing to verify the design. This large number many assertion has become unmanageable."

About Veritools

Veritools, Inc., is one of the leading providers of electronic design, debugging and verification tools. Founded in 1992, Veritools now provides its verification products to over 4,000 engineers in over 400 companies throughout the world. Headquartered in Palo Alto, California, Veritools is dedicated to making the fastest design, debugging and verification tools for designers who use Verilog, VHDL, Mixed Mode, and SystemVerilog. For more information please stop by our booth at the Design Automation Conference Booth #3651, or visit our web site at www.veritools.com

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