white paper

TOPIC: What does the VeritoolsVerifyer do?

With design verification taking more and more time of each ASIC project, and with the rate of first silicon success continuing to decline even further, Veritools is now focusing extensively on improving verification productivity with tools that provide a significant advance over what is on the market. These tools are aimed at providing improvements in verification productivity through the use of assertion-based verification with SystemVerilog Assertions. Not only can these tools significantly speed up verification but also they can provide to a much greater extent a full and complete verification of the design. In addition to verifying the design to a greater degree, these same tools can be used to give both designers and management a direct measure of the functional verification coverage for the very first time for a given design. These tools have also been extended to providing improved timing analysis for Gate designs.

How does the VeritoolsVerifyer do this?

The 100,000 lines of assertion code would break down to as many as 20,000 assertions. If a user has to rerun the design simulation every time there is an issue in one of the 20,000 assertions during the debug phase of their assertion testing the amount of time required to complete any design could be enormous. Using the "What If" window that is a part of this tools suite, users can either create new SVAssertion code or modify existing assertion code and then rerun the SVAssertion evaluation, which in most cases will take just a few seconds. Users are able to repeat this process many times in just a few minutes in order to thoroughly debug each assertion. The simulator only approach could take hours or perhaps even days to generate the same results, since the simulator is going to resimulate the entire design during each iteration, and in the process do millions and millions of redundant simulation operations since 99.99 percent of the simulation result files that had already been generated remain unchanged. Adding the evaluation of the SystemVerilog Assertions to the design simulation process, can also have a drastic and deleterious affect on simulation speed, since assertion evaluation is significantly different that design simulation, each and every assertion has to be re-evaluated at each and every clock, even if it is already in a process of being evaluated.

For an entire ASIC effort, using a batch evaluation process with a stand alone SystemVerilog Assertion evaluation engine can not only save many months of time in the overall effort to verify any given ASIC design, but it will produce a much more thorough level of design verification in the process. This can ensure a significantly higher rate of first silicon success than is presently available.

Waveform viewing for both analog and digital, with the most complete waveform viewer . Source code debugging with signal value trace back or forward . Schematic viewing for RTL and/or Gate designs, with signal value trace back through any number of logic levels . State Diagram display and analysis . Control Flow Graph with signal value trace back through any number of logic levels . PLI/VPI/VHPI file output and compression to 1300 X over standard file formats . Perl scripting built in for user-defined extensibility of the software.

About Veritools

Veritools, Inc., is one of the leading providers of electronic design, debugging and verification tools. Founded in 1992, Veritools now provides its verification products to over 4,000 engineers in over 400 companies throughout the world. Headquartered in Palo Alto, California, Veritools is dedicated to making the fastest design, debugging and verification tools for designers who use Verilog, VHDL, Mixed Mode, and SystemVerilog. For more information please stop by our booth at the Design Automation Conference Booth #3651, or visit our web site at www.veritools.com