Veritools HDL Debugging Solutions

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TOPIC: Converstion with a Customer

Thank you for talking with me on the phone earlier this week.

Just to reiterate what I said on the phone, Veritools is focused on both design, debug, but now more than ever we are focused on design verification with our main focus on tools to improve the rate of your companies first silicon success. We do this by having stand alone software that supports SystemVerilog, and SystemVerilog Assertions with debug of the users SVAssertions using a powerful graphical waveform display integrated right with a source code debugging environment. We have focused on tools for designers using SystemVerilog Assertions because of the two major issues caused by using assertions in design verification.

Using SVAssertions today has resulted in two major issues:

#1. Debugging assertion code is very hard for most designers today.

First because SystemVerilog Assertions are not part of the design code, making debugging assertion code very hard to do. The Veritools SystemVerilog Assertion Analyzer allows the user to debug their assertions in a graphical waveform window that makes debugging assertion code very easy to use.

#2. Simulations speeds are adversely effected when designers evaluate their assertion code along with the design simulation.

This is because assertion evaluation is significantly different than design simulation. Each and every assertion has to be re-evaluated at each and every clock, even if it is already in a process of being evaluated. This has had a significant affect on simulator performance when the design simulation process is also doing the assertion evaluation.

Simulating the Verilog or VHDL design along with the assertion code has made the simulation times get much longer for any given simulation run.

With the VeritoolsVerifyer, designers can evaluate their assertions off line without using their deign simulation process to evaluate their assertion code. Using the Veritools software, you can run your simulations just as is today, your design can be Verilog, VHDL or SystemVerilog.

For an entire ASIC effort, the use a batch evaluation process with a stand-alone SystemVerilog Assertion evaluation engine can not only save an enormous amount of time in the overall effort to verify any given ASIC design, but because results are produced faster, can produce a much more thorough level of design verification, insuring a significantly higher rate of first silicon success with the very complex designs that are becoming the norm.

This set of tools offers the following advantages, visibility in viewing the users assertion code, fast evaluation of assertions, ease of use when debugging complex assertion code, much faster simulation speeds, and thy ability to edit and re-evaluate any assertion in seconds;

Using the VeritoolsVerifyer to evaluate SystemVerilog Assertions.

#1. SystemVerilog Assertions can be displayed right in the users design hierarchy, showing the user exactly where in the design their assertions are located. Assertions are first shown in the users design hierarchy in black text, exactly where each assertion is located.

#2. Then the user can evaluate all of the assertions, in the design, or in any module, or any single assertion. Users can then evaluate any assertion in any module, including sub-modules, or any single assertion. Once evaluated the assertion results are then color coded right in the design hierarchy. Yellow indicates vacuailuoly true, Green, the assertion passed, Red, the assertion failed. Any assertion can then be selected.

#3. SystemVerilog Assertion debugging is very quick and easy to do with a graphical environment which gives the users the ability to do the following:

After evaluation and color coding, any assertion can be selected to view the assertion "result" waveform.

The users can select any assertion execution cycle, and view any assertion evaluation "timing" waveform, by selecting the assertion execution cycle from the assertion result waveform.

The users can also view the signals that contributed to this assertion evaluation cycle.

The users can also view where the unique assertion threads are located for any given assertion. By selecting any given unique execution thread, users can then view the local variables that were used in this unique threads execution process. This level of visibility into the users assertion execution process, is unobtainable from any other tool set on the market today.

#4. SVAssertion evaluation can be taken out of the design simulation step, and done off line from the simulation process, allowing the users simulators to run significantly faster, as much as 10 - 50 times faster for designs with a large amount of SVAssertion code.

Even a small amount of assertion code can slow the deign simulation down by a factor of 2X. Users have found that some designs with large numbers of assertion statements can slow the simulation down by a factor of 100. With a stand-alone SystemVerilog Assertion evaluation tool, first the design simulation process speed is unaffected by the number of assertion statements the users is evaluating since they are not evaluated in the design simulation process but off line from the simulation process. Hence design simulation speeds are never affected, they will never be slowed down by the assertion evaluation process.

Secondly the actual SVAssertions evaluation can be done very quickly off line, since the SystemVerilog Assertion evaluation engine has been designed for just one purpose, the evaluation of the users assertions code at very high speeds, in many cases taking just seconds or minutes to do the evaluation.

#5. The SystemVerilog assertion software includes a "what if" window that allows users to bring up their assertion code, modify any part of it, and re-evaluate the new assertion in most cases in a fraction of a second.

Perhaps the biggest difference when using a stand alone assertion evaluation process, is that debugging assertions can be done hundreds of times faster than when using a simulation only approach.

In a simulator only approach users would have to:

  • Compile their source code including their SystemVerilog Assertion code
  • Compile their source code Run their design simulation from beginning to end
  • Get the waveform file
  • Find the assertions that fail For assertions have failed they have to
  • Find the assertions that failed the assertion evaluation
  • Edit their assertion source file
  • Recommit this new source code
  • Re-compile the new source code
  • Re-run their design simulation
  • Re-load the simulation results waveform file into their waveform tool
  • Go to and re-evaluate the results to see if the new assertion code worked or failed
  • Repeat this as many times as needed to fix all of the failing assertions

Each repeat of this process using a simulator to evaluate the assertions can take several hours.

Using theVeritools approach users can:

  • Run their design simulation without any SVAssertion code
  • Evaluate their SVAssertion code after simulation is completed in a off line process
  • For assertions that fail users can; Select the failed assertion
  • Edit the assertion to fix the issue with the assertion evaluation
  • Rerun the evaluation, the waveforms on the display will update instantly to the new results
  • Repeat this process, from the "edit step" as many times as needed to fix and verify all of the failing assertions

Each repeat of this process using the stand alone SVAssertion evaluator to evaluate the assertions can be done in a few seconds instead of hours

The "What-if" Window

In addition to the speed advantage of evaluating your assertion code out side of the simulation process, the major speed advantage from using this assertion verification software comes from the use of the "What if" window, that is part of this software.

Users can either create new SVAssertion code or can modify existing assertion code that has failed the evaluation step and then rerun the SVAssertion evaluation, which in most cases will take just seconds. For assertions that are failing, users can view the assertion code that is failing by just clicking on the assertion evaluation result in the design hierarchy.

By pressing on a single icon, users can then edit this assertion. By selecting another single icon, they can rerun the assertion evaluation and re-display the evaluation results.

New waveforms are created for both the assertion result waveform and the assertion timing waveform, and these replace the prior evaluation waveforms on the waveform display, without changing any other aspect of the display.

Typically, the entire process of re-evaluating the edited assertion and then replacing the waveforms on the users waveform display can be done in a fraction of a second. Users are able to repeat this process many times very quickly in order to thoroughly debug and then verify each assertion.

The simulator only approach requires much more time to generate the same results, since the simulator is forced to re-simulate the entire design during each assertion evaluation iteration step.

In the process of re-simulation the simulator will do hundreds of billions of redundant operations since the vast percentage of the simulation result files that had already been generated remains completely unchanged.

The user can run a design simulation without the SVAssertion evaluated in the simulation cycle and then do the SystemVerilog Assertion evaluation over and over as many times as needed to evaluate, debug and correct any issue with the assertions.

The speed of the assertion evaluation process has become a increasingly significant issue as the amount of assertion code has become larger.

Many companies today that are intensely using SystemVerilog Assertions in their verification process have designs and ASIC projects with well over 100,000 lines of assertion code per chip.

This much SVAssertion code is essential just to be able to ensure a sufficiently high level of functional design correctness prior to tape out.

The 100,000 lines of assertion code breaks down to as many as 20,000 assertions. If users are forced to re-run the design simulation multiple times for each assertion in order to correct and then verify each of these 20,000 assertions during the debug phase of their assertion testing, and go through a process that requires several hours, instead of just seconds, for each iteration multiple times per each assertion, the amount of time required to complete the testing of the design using SVAssertions could be quite large.

This however is the situation many companies and designers are faced with today.

The result is the tape out date is determined not by having completed the entire verification process, but by management selecting an arbitrary schedule cut off point, in order to get the new design to market, before they loose the market window. Unfortunately this has been the reason that many companies have experienced low numbers for their first silicon success rates, and have had many designs that required design updates to fix functional errors.

In the end this not only does not make the market window, but in many cases causes the design to completely miss the market. As more and more SystemVerilog assertion code becomes integrated into the design process, a simulator only approach to verify the design assertion code will almost certainly make it increasingly more difficult to guarantee that these designs are sufficiently tested in time for the scheduled tape out step.

Functional Coverage

In addition these tools support SystemVerilog Assertion function verification coverage so users and managers can for the first time quickly get an accurate measure of exactly how much of their design has been functionally tested. Design managers can quickly see if a sufficient level of functional verification coverage has been reached in order to go on to tape out.

Assertions with Gate designs

Veritools will be also be adding to these tools features that will be focused on verifying the design at the gate level with essentially the same SystemVerilog Assertions that had been used to verify the RTL design, and using analog simulation results for a much higher accuracy when using your RTL assertions to verify your gate design. If these tools are of interest to you and your company, we can provide you a demo, and also an evaluation license. Thanks for your time and please let us know how I can further help you out. Best regards,

Bob Schopmeyer

About Veritools

Veritools, Inc., is one of the leading providers of electronic design, debugging and verification tools. Founded in 1992, Veritools now provides its verification products to over 4,000 engineers in over 400 companies throughout the world. Headquartered in Palo Alto, California, Veritools is dedicated to making the fastest design, debugging and verification tools for designers who use Verilog, VHDL, Mixed Mode, and SystemVerilog. For more information please stop by our booth at the Design Automation Conference Booth #3651, or visit our web site at

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