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A clocking domain can define detailed skew information for the relationship between a clock and one or more signals. Input skews specify the amount of time before a clock edge that signals should be sampled by a testbench. Output skews specify how many time units after a clock edge that signals should be driven. Note that "input" and "output" are relative to the testbench "that is, an output of the design under test is an input to the testbench. For example: 
In regular Verilog, which does not have clocking domains, the "initial" procedure in the preceding example would have race conditions with the design under test if the design is using the same positive edge of the clock to store values in registers. By using SystemVerilog clocking domain skews, the testbench can reference a clock edge to sample a value or drive stimulus. The appropriate skew will automatically be applied, thus avoiding race conditions with the design. Clocking domains greatly simplify defining a testbench that does not have race conditions with the design being tested. Direct Programming Interface (DPI). SystemVerilog provides a means for SystemVerilog code to directly call functions written C, C++ or SystemC, without having to use the complex Verilog Programming Language Interface (PLI). Values can be passed directly to the foreign language function, and values can be received from the function. The foreign language function can also call Verilog tasks and functions, which gives the foreign language functions access to simulation events and simulation time. The SystemVerilog DPI provides a bridge between high-level system design using C, C++ or SystemC and lower-level RTL and gate-level hardware design. Is SystemVerilog ready for use? Savvy engineers will have no doubt seen many SystemVerilog features in this article that will help them in their design and verification work. This, then, raises two important questions: "Is this new SystemVerilog standard really ready for software companies to implement, and how soon will software tools supporting SystemVerilog be available?" The answer to "Is the SystemVerilog standard ready?" is a resounding YES! The many experts from EDA companies and the Verilog user community that participated in the development of SystemVerilog have voted that the standard is ready to be released. Their recommendation, along with the SystemVerilog 3.1 Language Reference Manual, has been sent to the Accellera board of directors for final approval. The Board will be voting in late May 2003 on ratifying SystemVerilog 3.1. A subset of SystemVerilog which focused primarily on enhanced hardware modeling constructs was approved by the Accellera board in June of 2002, and released to EDA vendors as SystemVerilog 3.0. As to "When will software tools support SystemVerilog?", there are two answers. First, several EDA vendors are aggressively adding SystemVerilog to their existing Verilog tool sets. Look for some exciting product announcements and suite demonstrations at the upcoming Design Automation Conference (June 2-6 in Anaheim, California). Second, since most of the SystemVerilog extensions come from proven technology in commercial software tools, you are quite likely already using portions of SystemVerilog in your current designs, just under the guise of other proprietary names. It is worth noting that one EDA company on the Accellera board has raised a number of concerns regarding the current state of the SystemVerilog standard, and feels SystemVerilog should not be released at this time. The concerns that have been expressed are not against extending Verilog, but rather about the syntax or semantics of the extensions. The Accellera SystemVerilog committee has thoroughly analyzed all of the concerns expressed, and found no reason to delay the release of the SystemVerilog standard. A small number of the concerns are legitimate, and are being addressed by the SystemVerilog committee. Many of this company's concerns are in regard to the difficulty of implementing certain SystemVerilog constructs. Since SystemVerilog is based on donations of proven technology, and since other EDA vendors either have implemented, or are implementing these SystemVerilog constructs, the concern about the difficulty level is largely unfounded. It is never a simple task to retrofit old software products with new features, but that is no reason to not provide users with essential new language features. Most of the concerns expressed by this EDA company have to do with how certain enhancements are specified syntactically or semantically. For example, should the new int, byte and other data types be keywords or built-in object classes? These concerns are simply a matter of there being more than one good way to do the same thing. The majority of EDA companies and designers on the SystemVerilog committees voted to use one approach, while this one EDA vendor would have preferred a different approach. Concerns of this nature are simply a matter of preference, and have no bearing on the worthiness, correctness or readiness of the SystemVerilog standard. Conclusion. SystemVerilog provides a major set of extensions to the Verilog-2001 standard. These extensions allow modeling and verifying very large designs more easily and with less coding. By taking a proactive role in extending the Verilog language, Accellera is providing a standard that can be implemented by simulator and synthesis companies quickly. It is expected that the IEEE Verilog standards group will adopt the SystemVerilog extensions as part of the next generation of the IEEE 1364 Verilog standard. SystemVerilog extends the modeling aspects of Verilog, and adds a Direct Programming Interface which allows C, C++, SystemC and Verilog code to work together without the overhead of the Verilog PLI. SystemVerilog bridges the gap between hardware design engineers and system design engineers. SystemVerilog also significantly extends the verification aspects of Verilog by incorporating the capabilities of Vera and powerful assertion constructs. Adding these SystemVerilog extensions to Verilog creates a whole new type of engineering language, an HDVL, or Hardware Description and Verification Language. This unified language will greatly increase the ability to model huge designs, and verify that these designs are functionally correct. The SystemVerilog standard is ready for you to use, and several EDA companies are working on adding the SystemVerilog extensions to their Verilog software tools. References "SystemVerilog 3.1, ballot draft: Accellera's Extensions to Verilog", Accellera, Napa, California, April 2003. "Verilog 2001: A Guide to the new Verilog Standard", Stuart Sutherland, Kluwer Academic Publishers, Boston, Massachusetts, 2001. Stuart Sutherland is a member of the Accellera SystemVerilog technical subcommittee that is defining SystemVerilog, and is the technical editor of the SystemVerilog Language Reference Manual. He is also a member of the IEEE 1364 Verilog Standards Group, where he serves as chair of the PLI task force. Mr. Sutherland is an independent Verilog consultant, and specializes in providing comprehensive expert training on Verilog, SystemVerilog and the PLI. Mr. Sutherland can be reached by e-mail at stuart@sutherland-hdl.com. |
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