veritools solutions

A significant paradigm shift has now rendered virtually all prior design/debug/verification processes obsolete.

The major issue that has emerged for the 21 century, has been how to get first silicon success with Asics that getting ever more complex with more transistors more complex interfaces. During the last several years first silicon success has dramatically gone down from around 70% in 1995 to around 30% today. What is even worse is that that this downward trend in first silicon success is still in the process of going down. For the first time in recent history, design techniques are emerging that are targeted at reversing this decline in first silicon success. The Veritools software has always been focused on how to add productivity to the design process in a cost effective manner in order to achieve the highest possible success of the ASIC design process.

Veritools verification toolsr have evolved from being the fastest and most popular waveform viewer on the market with waverform viewing for both digital, and analog waveforms to include a complete suite of source code debugging tools. These tools included windows for displaying and editing source code, windows to display the users schematics, schematics of either RTL source code or gate netlists, and windows to display the users state diagrams which were extracted automatically from the users RTL source code. All of these windows are synchronized in time and use the drag and drop to so users can see different veiws of the design elements at the same time point in their simulation.

The current version of VeritoolsVerifyer and VeritoolsDesigner, supports both the complete URL definition of Verilog and VHDL.

This powerful tool is differentailted in three main areas;

(1) Complete schematic redering of the users RTL source code

While this set of software offers the the same set of source code debugging facilities as similar products on the market, such as multiple source code windows with driver and load trace back, multiple waveform, state diagram and schematic windows, this software is unique in offering a complete redering of the users RTL source code into complete and detailed schematics. Other software products in this market only provide a "Function" window for the lowest level schemtics, and when the users double clicks into this "Function" block a text window ids brought up with the source code in this "Function" Block is displayed in text. This means that the user now must return to a text process in order to attampt to undertsand this design. Part of the design is rendered in blocks and the rest is rendered in text windows, almost completely negating the use of schematics to understand and trace back their design using a schematic approach.

The VeritoolsDesigner provides as part of the tool set at no additional cost, a complete rendering of the users schematic, right down to each and every RTL elemnt represented as primative RTL gate in schematiuc form conected into the design structure as defined by the users RTL source code. This means that the drivers for every RTL elemnet are shown as RTL elements connected via wires from the loads of the prior element. Finding any driver for a RTL elemnts is as simple as flollowing the connections, or wires as shown on the schematic backwards to the driver RTL element. Since the waveform values for the time that the T0 cursor on the waveform window is at, are all annotated directly onto the schematic, users can see immediately exacly what path is causing the issue with their design and trace this back to RTL circuit that is causing the issue. Then with drag and drop see where this eleemnt is called out right in the source code in the source code window. This tools even lets the users press "Edit Source Code " at this point in ordedr to fix what ever issue might exist in the users source code at this point.

Nothing could make RTL debugging any faster or easier.

The original source of the error identification could have come from the user analysing their waveform on the waveform window, or from analysing the signal values annotated dirctly onto the source code window, or from viewng the automatuically extracted state diagrams and finding a state that was not correct.

Tracing can even take place across multiple clock edges, automatically, using the "Trace Back" icon.

Speed of the waveform and schematic viewing

Cost effective

The new version of our tools, supports, in addition to all of the features of VeritoolsDesigner, SystemVerilog. VeritoolsVerifyer supports the complete elaboration of the SystemVerilog language so that users can display their RTL schematics for increased understanding of their complex SystemVerilog designs. Tsunami also supports the complete URL specifcation of the SystemVerilog Assertions extention to SystemVerilog.

Current Asics of today of even modest complexity can require 30,000 lines of assertion code, new Asics are expected to require over 100,000 lines of complex assertion software code.

The verification process that would require designers days or even weeks to do using a simulation only process itself could be done in a matter of hours using the completely new and patented Veritools assertion verification process.

These issues are detailed in the following descriptions of the software functionality for doing "Functional Verification" and "Functional Verification Coverage".

Functional Verification

Issues

Complexity

Design size

Waveform file output size

First silicon success

Source Code Debugging Environment

Design

VHDL

Verilog

SystemVerilog

Debugging

Visualization

Speed

Cost effective

Functional Verification Coverage

Assertions

Issues

Current Asics of today of even modest complexity can require 30,000 lines of assertion code, new Asics are expected to require over 100,000 lines of complex assertion software code.

The verification process that would require designers days or even weeks to do using only a simulation process by itself can be done in a matter of hours using the completely new and patented Veritools verification process "Raptor".

Verification Coverage

IP Security