caliper tool

Veritools products are available on: Solaris 32/64, HP 32/64, AIX32, Linux 32 and Windows!

a batch tool for running HSpice Measure scripts

Description Here.

Benefits

• Detect clock domain synchronization errors
  
• Detect races before simulation
  
• Automatically check design re-usability
  
• Enforce your design methodology
  
• Find design for testability errors at RTL stage
  

Hundreds of Rules...

• Race detection
  
• Write-Write
  
• Read-Write
  
• Latch-Latch
  
• Combinational loop
  
• Clock gating races
  
• Clock Domain Boundary Checks
  
• Clock domain boundary crossings
  
• Synchronization of data
  
• Use of specified synchronization cells
  
• Design reuse methodology
  
• Coding style
  
• Reuse Methodology Manual (RMM)
  
• Synthesis checks
  
• Simulation-synthesis mismatches
  
• Synthesis compatibility
  
• Implied latches
  
• Testability checks
  
• RTL ATPG checks
  
• Clock gating
  
• Asynchronous sets/resets
  
• Asynchronous clocks
  
• Net-list checks
  
• X-source problems
  
• Redundant logic
  
• Conflicting assignments
  
• Range Violation
  
• Non-resetable flip-flops