Veritools HDL Debugging Solutions

v lint tool

Veritools products are available on: Solaris 32/64, HP 32/64, AIX32, Linux 32 and Windows!
Veritools Supported Platforms

VLint: a formal predictive lint checker

VLint is an innovative predictive RTL analysis tool that simplifies and speeds up design checking using a combination of formal and structural analysis. VLint eliminates complex design errors at all stages of your design implementation cycle from RTL to gate level, from module to full chip level.


  • Detect clock domain synchronization errors
  • Detect races before simulation
  • Automatically check design re-usability
  • Enforce your design methodology
  • Find design for testability errors at RTL stage

Hundreds of Rules...

  • Race detection
  • Write-Write
  • Read-Write
  • Latch-Latch
  • Combinational loop
  • Clock gating races
  • Clock Domain Boundary Checks
  • Clock domain boundary crossings
  • Synchronization of data
  • Use of specified synchronization cells
  • Design reuse methodology
  • Coding style
  • Reuse Methodology Manual (RMM)
  • Synthesis checks
  • Simulation-synthesis mismatches
  • Synthesis compatibility
  • Implied latches
  • Testability checks
  • RTL ATPG checks
  • Clock gating
  • Asynchronous sets/resets
  • Asynchronous clocks
  • Net-list checks
  • X-source problems
  • Redundant logic
  • Conflicting assignments
  • Range Violation
  • Non-resetable flip-flops
“Use VLint to eliminate design errors earlier and be immediately more productive."
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